Sensing operations, which read or otherwise determine the states of memory cells in semiconductor memory devices, often use a reference signal and generate a data value depending on the relation of a bit line signal to the reference signal. The bit line signal generally depends on a current through or from a memory cell connected to the bit line and is subject to variations in the performance of the memory cell. Such performance variations may arise from variations in the fabrication process for the memory, the temperature or other operating conditions, the endurance or cycling history, the age of the memory cell, or the lapsed time since data was written to the memory cell. The reference signal preferably tracks these performance variations of the memory cell so that sensing operations provide consistent results, i.e., output the same data value, despite the variations.
FIG. 1 illustrates a conventional bit line reference scheme for a conventional Flash memory array 100 using a single-ended sense amplifier 150. Flash memory array 100 has a separate bank 110 of reference cells 115 that are substantially identical to and operate in the same manner as memory cells 125 in a bank 120. Reference memory cells 115, in this example, are set at an “erased” or “low” threshold voltage (Vt) state.
FIG. 1 shows memory cells 125 and reference memory cells 115 sharing the same word lines WL1 to WLn and word line drivers 140. In general, using the same word lines for memory and reference cells provides better tracking of gate or word line voltages and eliminates the need for separate reference word line decoders and drivers and associated redundancy circuits. In a standby mode of memory array 100, all word lines WL1 to WLn are grounded to turn off all memory cells 125 so that little or no bit line current flows, and single-ended sense amplifier 150 (and its output signal SAout) are set to a state that corresponds to reading a “programmed” or “high Vt” memory cell.
For a sensing operation, a selected word line driver 140 activates a selected word line. As a result, an activated reference cell 115 provides a reference current on a reference bit line BLref. The reference current is preferably about equal to the normal cell current through a virgin or low Vt memory cell in memory array 120. Selected memory cells 125 that are connected to the activated word line conduct or not depending upon the threshold voltage states of the memory cells.
P-channel pull-up devices 131 and 132 connected in a “current-mirror” configuration mirror the reference current from reference bit line BLref to bit lines BLm. As a result, the ratio of the sizes of P-channel pull-up devices 131 and 132 determines the percentage of the normal cell current that a selected memory cell 125 must conduct to trip the corresponding sense amplifier 150. Typically, this ratio ranges from about 2:1 to 4:1, (e.g., W1/L1 is between 2W2/L2 and 4W2/L2, where transistor 131 has channel width W1 and channel length L1 and transistor 132 has channel width W2 and channel length L2. If the ratio is 4:1, and if the normal cell current through a virgin or low Vt reference cell is 40 μA, the selected memory cell must conduct more than 10 μA to trip single-ended sense amplifier 150, causing output signal SAout to represent the data value “1.” Accordingly, a virgin or low Vt memory cell, which conducts a current greater than 10 μA will trip single-ended sense amplifier 150, but a programmed memory cell, which conducts a current less than 10 μA, does not trip sense amplifier 150, causing output signal SAout to represent the data value “0.”
FIG. 2 shows a contactless buried diffusion memory array 200 implementing a sensing operation that uses a reference signal and single-ended sense amplifier 150 in the same manner as described above for memory array 100 of FIG. 1. Memory array 200 has a bank 210 of reference cells 215, a bank 220 of memory cells 225, and bit line pull-up devices 131 and 132. In particular, the activated reference cell 215 conducts a reference current on reference bit line BLref that is about equal to the normal current through a virgin or low Vt memory cell, and bit line pull-up devices 131 and 132 mirror the reference current to bit lines BLm. Single-ended sense amplifiers 150, which are connected to the bit lines BLm, will trip or not depending on whether or not selected memory cells 225 conduct a current greater than the mirrored current.
FIG. 3 illustrates a conventional Flash memory array 300 implementing a conventional bit line reference scheme for a sense amplifier 350 having differential inputs. In memory array 300, reference cells 115 in separate reference bank provides a reference-current approximately equal to a “½ cell reference current”, which is about half-way between the current through a memory cell in the erased or low Vt state and a “zero cell current” through a memory cell 125 in the programmed or high Vt state. Memory array 300 uses two P-channel bit line pull-up devices 331 and 332 that differ from devices 131 and 132 of FIG. 1 in that devices 331 and 332 have approximately the same sizes and are not connected to form a current-mirror. Additionally, a common Vbias voltage, which can be a reference voltage having a voltage level lower than Vcc minus the threshold voltage Vtp of a pull-up device, controls P-channel bit line pull-up devices 331 and 332. Accordingly, in memory array 300, bit line pull-up devices 331 and 332 conduct the same or nearly the same amount of current.
A voltage difference that develops between bit line BLm and reference bit line BLref is positive or negative depending on whether the selected memory cell 125 conducts less or more current than the selected reference cell 115 conducts. Differential sense amplifier 350 can sense a small voltage difference that develops between the I/O and I/O reference lines that are connected to the selected bit line BLm and the reference bit line BLref. Sense amplifiers 350 with differential inputs generally provide faster sensing than do single-ended sense amplifiers 150 (FIGS. 1 and 2). In addition, sense amplifiers 350 with differential inputs generally provide better tracking performance and noise cancellation due to the inherent “differential” input and output paths.
A difficulty in memory array 300 relates to the generation of the “½ cell reference current” that is about half the normal current through a virgin memory cell. FIG. 3 shows a common approach having reference word lines RWL1 to RWLn that are physically separated from the normal word lines WL1 to WLn. For a sensing operation, drive circuits 340 associated with reference word lines RWL1 to RWLn activate a selected reference word line using a voltage VR2 that is lower than the normal word line voltage VR1, (e.g., VR2 is about ½ VR1), in order to generate the “½ cell current”. During programming, reference word lines RWL1 to RWLn typically remain “low” because the reference memory cells 115 typically remain in the erased or low Vt state.
FIG. 4 illustrates a contactless memory 400 that implements the reference techniques of FIG. 3 in a contactless memory architecture. Memory array 400 like memory array 300 employs word lines WL1 to WLn that are separate from reference word lines RWL1 to RWLn, and the difference in the bias voltages VR1 and VR2 respectively on the selected word lines and the selected reference word line causes the selected reference cell 215 to conduct only the desired “½ cell reference current.”
The reference scheme of FIGS. 3 and 4 requires a substantial amount of supporting circuits, silicon area, power consumption, and increased circuit complexity. Typical required additional supporting circuits (not shown) include: a “precision” reference word line voltage generator; reference word line decoders and driver circuits, which are typically located at an end of the array opposite to the normal word line decoders and drivers; and reference word line redundancy circuits for the reference word line decoders and drivers. For this reference scheme, selection of the reference word line (and bank selects in memory array 500) preferably matches the location of the selected normal word line, in order to track the source line resistance and/or buried diffusion bit line and source line resistances, as well as the memory cell orientation effect. However, reference word lines RWL1 to RWLn physically differ from normal word lines WL1 to WLn, and the reference cells 115 or 215 cannot achieve 100% tracking with memory cells 125 or 225. For example, making the voltage levels for reference cells 115 or 215 perfectly track the corresponding voltage levels for memory cells 125 or 225 for temperature, supply voltage Vcc, and process variations would be very difficult or impossible. Also, the reference cells 115 and 215 experience disturb effects that differ from disturb effects on normal memory cell 125 or 225, and references cells 115 or 215 do not track the endurance cycling and aging effects on memory cells 125 or 225.
In view of the limitations of current referencing techniques for sensing operations, circuits and processes that provide good tracking of memory cell performance and fast sensing without undue power consumption or circuit complexity are sought.